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? 2016 microchip technology inc. ds20005624a-page 1 dsc61xx features ? wide frequency range: 2 khz to 100 mhz ? ultra?low power consumption: 3 ma/12 ? a (active/standby) ? ultra-small footprints - 1.6 mm ? 1.2 mm - 2.0 mm ? 1.6 mm - 2.5 mm ? 2.0 mm - 3.2 mm ? 2.5 mm ? frequency select input supports 2 predefined frequencies ? high stability: 25, 50 ppm ? wide temperature range - industrial: ?40c to 85c - ext. commercial: ?20 to 70c ? excellent shock & vibration immunity - qualified to mil-std-883 ? high reliability - 20x better mtf than quartz oscillators ? supply range of 1.71v to 3.63v ? short sample lead time: <2 weeks ? lead free & rohs compliant applications ? low power/portable applications - iot, embedded/smart devices ? consumer - home healthcare, fitness devices, home automation ? automotive - rear view/surround view cameras, infotainment system ? industrial - building/ factory automation, surveillance camera general description the dsc61xx family of mems oscillators combines the industry leading low power consumption and ultra-small packages with exceptional frequency stability and jitter performance over temperature. the single-output dsc61xx mems oscillators are excellent choices for use as clock references in small, battery-powered devices such as wearable and internet of things (iot) devices in which small size, low power consumption, and long-term reliability are paramount. they also meet the stringent mechanical durability and reliability requirements within automotive electronics council standard q100 (aec-q100), so they are well suited for under-hood applications as well. the dsc61xx family is available in ultra-small 1.6 mm x 1.2 mm and 2.0 mm x 1.6 mm packages. other package sizes include: 2.5 mm x 2.0 mm and 3.2 mm x 2.5 mm. these packages are ?drop-in? replacements for standard 4-pin cmos quartz crystal oscillators. package types dsc61xx 3.2x2.5 dfn top view dsc61xx 2.5x2.0 lga top view dsc61xx 2.0x1.6 lga top view dsc61xx 1.6x1.2 lga top view 12 3 4 12 3 4 12 43 12 3 4 ultra-small, ultra-low power mems oscillator
dsc61xx ds20005624a-page 2 ? 2016 microchip technology inc. block diagram dsc6101/02/11/12/21/22/41/42/51/52/61/62 dsc6183 (khz output) mems resonator temp sensor control & compensation pll vco output divider driver supply regulation p1 output p2 gnd p4 vdd p3 dnc mems resonator temp sensor control & compensation pll vco output divider driver supply regulation pin 1 oe/stby/fs pin 2 gnd pin 4 vdd pin 3 output digital control
? 2016 microchip technology inc. ds20005624a-page 3 dsc61xx 1.0 electrical characteristics absolute maximum ratings supply voltage ................................................................................................................. ......................... ?0.3v to +4.0v input voltage, v in ............................................................................................................................... ?0.3v to v dd +0.3v esd protection .......................................................................................................4000v hbm , 400v mm, 2000v cdm dsc61xx electrical characteristics electrical characteristics: unless otherwise indicated, v dd = 1.8v ?5% to 3.3v +10%, t a = ?40c to 85c. parameters sym. min. typ. max. units conditions supply voltage, note 1 v dd 1.71 ? 3.63 v ? active supply current i dd ? 3.0 ? ma f out = 27 mhz, v dd = 1.8v, no load standby supply current note 2 i stby ?12 ? ? a v dd = 1.8/2.5v ?80 ? v dd = 3.3v frequency stability note 3 f?? 25 50 ppm all temp ranges aging f ?? 5 ppm 1st year @25c ? ? 1 per year after first year startup time t su ? ? 1.3 ms from 90% v dd to valid clock output, t = 25c input logic levels note 4 input logic high input logic low v ih 0.7xv dd ?? v ? v il ? ? 0.3xv dd v output disable time note 5 t da ? ? 200+period ns ? output enable time note 6 t en ?? 1 ? s? enable pull-up resistor note 7 ? ? 300 ? k ? if configured output logic levels output logic high output logic low v oh 0.8xv dd ? ? v i = 6ma v ol ? ? 0.2xv dd v i = ?6ma note 1: pin 4 v dd should be filtered with 0.1 uf capacitor. 2: not including current through pull-up resistor on en pin (if configured). higher standby current seen at >3.3v v dd . 3: includes frequency variations due to initial tolerance, temp. and power supply voltage. 4: input waveform must be monotonic with rise/fall time < 10 ms 5: output disable time takes up to 1 period of the output waveform + 200 ns. 6: for parts configured with oe, not standby. 7: output is enabled if pad is floated or not connected.
dsc61xx ds20005624a-page 4 ? 2016 microchip technology inc. output transition time rise time/fall time t rx /t fx ? 1 1.5 ns dsc61x2 high drive, 20% to 80% c l =15 pf v dd = 1.8v ? 0.5 1.0 ns v dd = 2.5v/3.3v t ry /t fy ? 1.2 2.0 ns dsc61x1 std drive, 20% to 80% c l =10 pf v dd = 1.8v ? 1.5 2.2 ns v dd = 2.5v/3.3v frequency f 0 0.002 ? 100 mhz output on pin 1 for < 1 mhz output duty cycle sym 45 ? 55 % ? period jitter, rms j per ? 9.5 11 ps rms f out = 27 mhz v dd = 1.8v ? 7.5 9 v dd = 2.5v/3.3v cycle-to-cycle jitter (peak) j cy?cy ?50 70 ps f out = 27 mhz v dd = 1.8v ?35 60 v dd = 2.5v/3.3v dsc61xx electrical characteristics (continued) electrical characteristics: unless otherwise indicated, v dd = 1.8v ?5% to 3.3v +10%, t a = ?40c to 85c. parameters sym. min. typ. max. units conditions note 1: pin 4 v dd should be filtered with 0.1 uf capacitor. 2: not including current through pull-up resistor on en pin (if configured). higher standby current seen at >3.3v v dd . 3: includes frequency variations due to initial tolerance, temp. and power supply voltage. 4: input waveform must be monotonic with rise/fall time < 10 ms 5: output disable time takes up to 1 period of the output waveform + 200 ns. 6: for parts configured with oe, not standby. 7: output is enabled if pad is floated or not connected.
? 2016 microchip technology inc. ds20005624a-page 5 dsc61xx temperature specifications parameters sym. min. typ. max. units conditions temperature ranges junction operating temperature t j ? +150 ? c ? storage temperature range t a ?55 ? +150 c ? soldering temperature t s ? +260 ? c 40 sec. max.
dsc61xx ds20005624a-page 6 ? 2016 microchip technology inc. 2.0 pin descriptions the descriptions of the pins are listed in table 2-1 . note 1: dsc610x/1x/2x has 300 k internal pull-up resistor on pin1. dsc614x/5x/6x has no internal pull-up resistor on pin1 and needs external pull-up or being driven by other chip. 2: two pre-programmed frequencies can be configured at http://clockworks.microchip.com/timing/ 3: bypass with 0.1 f capacitor placed as close to v dd pin as possible. note 1: bypass with 0.1 f capacitor placed as close to v dd pin as possible. dsc61xx family is available in multiple output driver configurations. the standard-drive (61x1) and high-drive (61x2) deliver respective output currents of greater than 3 ma and 6 ma at 20%/80% of the supply voltage. for heavy loads of 15 pf or higher, the high-drive option is recommended. table 2-1: dsc6101/03/11/13/21/23/41/43/51/53/61/63 pin function table (output frequency 1mhz) pin number pin name pin type description 1 oe i output enable: h = specified frequency output, note 1 l = output is high impedance stdby standby: h = specified frequency output, note 1 l = output is high impedance. device is in low power mode, supply current is at i stby fs frequency select: h = output frequency 1, note 2 l = output frequency 2 2 gnd power power supply ground 3 output o oscillator clock output 4 vdd power power supply table 2-2: dsc6183 pin function table (output frequency <1mhz) pin number pin name pin type description 1 output o kilohertz oscillator clock output 2 gnd power power supply ground 3 dnc dnc do not connect 4 vdd power power supply, note 1
? 2016 microchip technology inc. ds20005624a-page 7 dsc61xx 3.0 output waveform figure 3-1: output waveform v oh v ol v il 1/f o outpu t enable t da t en t f t r v ih
dsc61xx ds20005624a-page 8 ? 2016 microchip technology inc. 4.0 test circuit figure 4-1: test circuit 3 4 2 1 c l
? 2016 microchip technology inc. ds20005624a-page 9 dsc61xx 5.0 board layout (recommended) figure 5-1: board layout (recommended)
dsc61xx ds20005624a-page 10 ? 2016 microchip technology inc. 6.0 solder reflow profile figure 6-1: solder reflow 60-150 sec 20-40 sec 60-180 sec 8 min max pre heat re?w cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60-150 sec 20-40 sec 60-180 sec 8 min max pre heat re?w cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60-150 sec 20-40 sec 60-180 sec 8 min max pre heat re?w cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. msl 1 @ 260 c refer to jstd-020c ramp-up rate (200c to peak temp) 3c/sec max. preheat time 150c to 200c 60-180 sec time maintained above 217c 60-150 sec peak temperature 255-260 c time within 5c of actual peak 20-40 sec ramp-down rate 6c/sec max. time 25c to peak temperature 8 min. max.
? 2016 microchip technology inc. ds20005624a-page 11 dsc61xx 7.0 packaging information 4-lead vflga 1.6 mm x 1.2 mm package outline 0.07 c a b 0.03 c (datum b) (datum a) c seating plane note 1 12 n top view side view bottom view note 1 12 n 0.10 c 0.08 c microchip technology drawing c04-1199a sheet 1 of 2 4x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 4-lead very thin fine pitch la nd grid array (ara) - 1.6x1.2 mm body [vflga] d e b a 0.05 c 0.05 c 2x 2x 4x l b2 e ch ch a (a3) a1 e1 e1 2 3x b1
dsc61xx ds20005624a-page 12 ? 2016 microchip technology inc. 4-lead vflga 1.6 mm x 1.2 mm package outline microchip technology drawing c04-1199a sheet 2 of 2 ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m 4-lead very thin fine pitch la nd grid array (ara) - 1.6x1.2 mm body [vflga] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height overall width terminal length substrate thickness (with terminals) terminal pitch standoff units dimension limits a1 a b2 a3 e l e n 1.20 bsc 0.20 ref 0.325 0.30 0.79 0.00 0.35 0.375 0.84 0.02 1.20 bsc millimeters min nom 4 0.425 0.40 0.89 0.05 max ch 0.125 -- terminal 1 index chamfer overall length d 1.60 bsc terminal width b1 0.25 0.30 0.35 terminal width terminal pitch e1 0.75 bsc
? 2016 microchip technology inc. ds20005624a-page 13 dsc61xx 4-lead vflga 1.6 mm x 1.2 mm recommended land pattern recommended land pattern dimension limits units x2 contact width contact pitch millimeters 1.20 bsc min e1 max space between contacts (x4) contact pad length (x6) g1 y0.50 microchip technology drawing c04-3199a nom 4-lead very thin fine pitch land grid array (ara) - 1.6x1.2 mm body [vflga] silk screen 12 4 x1 contact width (x3) space between contacts (x3) g2 0.25 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m 1. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: x1 y g2 (ch) c contact spacing 0.75 0.43 0.35 0.85 contact 1 index chamfer ch 0.13 x 45 ref c e2 contact pitch 1.16 bsc e2 x2 g1 e1
dsc61xx ds20005624a-page 14 ? 2016 microchip technology inc. 4-lead vlga 2.0 mm x 1.6 mm package outline 0.07 c a b 0.03 c (datum b) (datum a) c seating plane note 1 12 n top view side view bottom view note 1 12 n 0.10 c 0.08 c microchip technology drawing c04-1200a sheet 1 of 2 4x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 4-lead very thin fine pitch land grid array (asa) - 2.0x1.6 mm body [vflga] d e b a 0.05 c 0.05 c 2x 2x 4x l b2 e ch ch a (a3) a1 e1 e1 2 3x b1
? 2016 microchip technology inc. ds20005624a-page 15 dsc61xx 4-lead vlga 2.0 mm x 1.6 mm package outline (continued) microchip technology drawing c04-1200a sheet 2 of 2 ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m 4-lead very thin fine pitch land grid array (asa) - 2.0x1.6 mm body [vflga] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height overall width terminal length substrate thickness (with terminals) terminal pitch standoff units dimension limits a1 a b2 a3 e l e n 1.55 bsc 0.20 ref 0.40 0.50 0.79 0.00 0.55 0.45 0.84 0.02 1.60 bsc millimeters min nom 6 0.50 0.60 0.89 0.05 max ch 0.15 -- terminal 1 index chamfer overall length d 2.00 bsc terminal width b1 0.30 0.35 0.40 terminal width terminal pitch e1 0.95 bsc
dsc61xx ds20005624a-page 16 ? 2016 microchip technology inc. 4-lead vflga 2.0 mm x 1.6 mm package outline recommended land pattern dimension limits units x2 contact width (x2) contact pitch millimeters 1.55 bsc min e max space between contacts (x4) contact pad length (x6) g1 y0.70 microchip technology drawing c04-3200a nom 4-lead very thin fine pitch land grid array (asa) - 2.0x1.6 mm body [vflga] silk screen 12 4 x1 contact width (x4) space between contacts (x3) g2 0.25 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m 1. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: x1 y g2 g1 e (ch) c contact spacing 0.95 0.40 0.50 1.05 contact 1 index chamfer ch 0.13 x 45 ref c
? 2016 microchip technology inc. ds20005624a-page 17 dsc61xx 4-lead vlga 2.5 mm x 2.0 mm package outline 0.07 c a b 0.03 c (datum b) (datum a) c seating plane note 1 12 n top view side view bottom view note 1 12 n 0.10 c 0.08 c microchip technology drawing c04-1202a sheet 1 of 2 4x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 4-lead very thin land grid array (aua) - 2.5x2.0 mm body [vlga] d e b a 0.05 c 0.05 c 2x 2x 4x l e ch ch a (a3) a1 e1 e1 2 4x b1
dsc61xx ds20005624a-page 18 ? 2016 microchip technology inc. 4-lead vlga 2.5 mm x 2.0 mm package outline (continued) microchip technology drawing c04-1202a sheet 2 of 2 ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m 4-lead very thin land grid array (aua) - 2.5x2.0 mm body [vlga] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height overall width terminal length substrate thickness (with terminals) terminal pitch standoff units dimension limits a1 a a3 e l e n 1.65 bsc 0.20 ref 0.60 0.79 0.00 0.65 0.84 0.02 2.00 bsc millimeters min nom 4 0.70 0.89 0.05 max ch 0.225 -- terminal 1 index chamfer overall length d 2.50 bsc b1 0.60 0.65 0.70 terminal width terminal pitch e1 1.25 bsc
? 2016 microchip technology inc. ds20005624a-page 19 dsc61xx 4-lead vlga 2.5 mm x 2.0 mm recommended land pattern recommended land pattern dimension limits units contact pitch millimeters 1.65 bsc min e max space between contacts (x4) contact pad length (x6) g1 y0.80 microchip technology drawing c04-3202a nom 4-lead very thin land grid array (aua) - 2.5x2.0 mm body [vlga] silk screen 12 4 x contact width (x4) space between contacts (x3) g2 0.45 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m 1. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: x y g2 c e (ch) c contact spacing 1.25 0.70 0.95 contact 1 index chamfer ch 0.13 x 45 ref g1
dsc61xx ds20005624a-page 20 ? 2016 microchip technology inc. 4-lead cdfn 3.2 mm x 2.5 mm package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging title 4 lead cdfn 3.2x2.5mm col package outline & recommended land pattern drawing # cdfn3225-4ld-pl-1 unit mm not e: 1. green shaded rectangles in recommended land pattern are solder stencil opening.
? 2015 microchip technology inc. ds20005624a-page 21 dsc61xx appendix a: revision history revision a (september 2016) ? initial release of dsc61xx microchip data sheet ds20005624a.
dsc61xx ds20005624a-page 22 ? 2015 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005624a-page 23 dsc61xx product identification system to order or obtain information, e.g., on pricing or delivery, contact your local microchip representative or sales office . note 1: please visit microchip clockworks ? configurator website to configure the part number for customized fre- quency. http://clockworks.microchip.com/timing/. examples: a) dsc6112ji2a-100.0000: ultra?low power mems oscillator, pin1= standby with internal pull?up, high output drive strength, 4-lead 2.5 mm x 2.0 mm vflga, industrial tem- perature (?40c to +85c), 25 ppm, revision a, 100 mhz frequency, bulk. b) dsc6101he1a-016.0000t: ultra?low power mems oscillator, pin1= oe with internal pull?up, stan- dard output drive strength, 4-lead 1.6 mm x1.2 mm vflga, extended com- mercial temperature (?20c to +70c), 50 ppm, revision a, 16 mhz frequency, tape and reel. c) dsc6183me1a-032k768: ultra?low power mems oscillator, pin1= 32.768 khz clock output, low output drive strength, 4-lead 2.0 mm x1.6 mm vflga, extended com- mercial temperature (?20c to +70c), 50 ppm, revision a, bulk d) dsc6121ci2a-001a: ultra?low power mems oscillator, pin1= fs with internal pull-up, standard output drive strength, 4- lead 3.2 mm x 2.5 mm cdfn, industrial tempera- ture (-40 to 85c), 25 ppm, revision a, fre- quency code = 001a (con- figured through clockworks), bulk p art no. x package device device: dsc61xx: ultra-low power mems oscillator pin definition: selection pin 1 internal pull register 0 oe pull-up 1 stdby pull-up 2 fs pull-up 4 oe none 5 stdby none 6 fs none 8 khz output none output drive strength: 1 2 standard high packages: c = 4-lead 3.2 mm x 2.5 mm dfn j = 4-lead 2.5 mm x 2.0 mm vflga m = 4-lead 2.0 mm x 1.6 mm vflga h = 4-lead 1.6 mm x 1.2 mm vflga temperature range: e = -20 ? c to +70 ? c (extended commercial) i = -40 ? c to +85 ? c (industrial) frequency stability: 1 = 50 ppm 2 = 25 ppm revision: a = revision a frequency: xxx.xxxx = user-defined frequency between 001.0000 mhz and 100.0000 mhz xxxkxxx = user-defined frequency between 002.000 khz and 999.999 khz xxxx = frequency configuration code when pin 1 = fs. configure the part online through clockworks tape and reel: blank = bulk t = tape and reel x pin 1 definition note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. x output drive strength x temperature range x frequency stability x revision xxx.xxxx frequency x tape and reel ?
dsc61xx ds20005624a-page 24 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005624a-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, includ ing but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0961-8 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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